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HT6230 Infrared Remote Encoder
Features
* * * * *
Operating voltage: 2.4V~5.2V 32 system codes, each system with 64 command codes Programmable transmission codes Biphase transmission method Generated modulation output data
* * * *
(1/2 system frequency and 1/4 duty cycle) Single pin oscillator 429kHz resonator system clock Test pins available 28-pin SOP package
Applications
* *
Televisions and video cassette recorder controllers Garage door controllers
* * *
Car door controllers Security systems Other remote control systems
General Description
The HT6230 is designed as infrared remote encoder, usually applied to TV systems. A total of 2048 different commands can be generated and arranged into 32 systems where each system contains 64 different commands. There are 96 keys and to each key is assigned one programmable code. The code is programmable by mask option. Legal and illegal key operation can be distinguished.
Block Diagram
RC OSC 321
2 13
OSC
D iv id e r
P a r a lle l T o S e r ia l C o n v e rte r
TT1 TT2
Test M ode
R eset A c tio n G e n e ra to r
O u tp u t S ta g e
CODE
MS
M ode S e le c tio n
C o n tro l U n it Z -k e y PAL
M o d u la tio n O u tp u t S ta g e
MCODE
Z IN 3 Z IN 0 X IN 7
Z -k e y E ncoder
DRS7 Com m and And S y s te m C o d e L a tc h Z -D R S PAL X -D R S PAL K ey S can D r iv e r D ecoder DRS0
X -k e y E ncoder X IN 0
X -k e y PAL
VSS
VDD
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Pin Assignment
X IN 7 MS Z IN 0 Z IN 1 Z IN 2 Z IN 3 MCODE CODE DRS7 DRS6 DRS5 DRS4 DRS3 VSS 9 10 11 12 13 14 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD X IN 6 X IN 5 X IN 4 X IN 3 X IN 2 X IN 1 X IN 0 TT1 TT2 OSC DRS0 DRS1 DRS2
Pad Assignment
X IN 7 X IN 6 X IN 5 VDD X IN 4 Z IN 0 28 X IN 3 Z IN 1 1 MS 27
26
25
24
23
22
21 20 X IN 2 X IN 1 X IN 0 TT1 TT2
Z IN 2 2 3 4 Z IN 3 MCODE
19 18 (0 ,0 ) 5 6 7 17 16
CODE DRS7 DRS6
HT6230 28 SO P
DRS5
8 9
10 DRS3
11 VSS
12 DRS2
13 DRS1
14 DRS0
15 OSC
Chip size: 1605 1910 (mm) * The IC substrate should be connected to VDD in the layout artwork.
DRS4
2
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 X -570.19 -662.85 -662.85 -662.85 -662.85 -662.85 -662.85 -644.16 -429.58 -288.15 -98.77 107.68 249.11 463.69 Y 817.68 442.16 300.74 120.29 -147.93 -395.02 -536.45 -817.68 -817.68 -817.68 -817.68 -817.68 -817.68 -817.68 Pad No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 X 605.12 653.07 653.07 653.07 653.07 653.07 561.23 419.80 278.37 136.94 -4.48 -145.91 -287.34 -428.76
Unit: mm Y -817.68 -75.59 65.84 207.26 437.29 578.71 817.68 817.68 817.68 817.68 817.68 817.68 817.68 817.68
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Pad Description
Pad No. 1~3 28 4 5 6~10 11 12~14 15 Pad Name ZIN1~ZIN3 ZIN0 MCODE CODE DRS7~DRS3 VSS DRS2~DRS0 OSC I/O I O O O 3/4 O I Internal Connection Description
CMOS with Detect inputs from Z-key matrix PMOS Pull-high Tri-state CMOS Tri-state CMOS Open Drain NMOS 3/4 Open Drain NMOS CMOS Generate modulation output data code with 1/12 system frequency and 1/4 duty cycle Generates output data code Drive for key scanning Negative power supply, ground Drive for key scanning Oscillator input Switch to four operating modes: 0 0 normal mode 0 1 test mode 1 1 0 test mode 2 1 1 Reset
16~17
TT2~TT1
I
CMOS
18~24 25 26 27
XIN0~XIN6 VDD XIN7 MS
I 3/4 I I
CMOS with Detect inputs from X-key matrix PMOS Pull-high 3/4 Positive power supply CMOS with Detect input from X-key matrix PMOS Pull-high CMOS Select system mode (Two modes provided: One-key system mode and Two-key system mode)
Approximate internal connection circuits
* Input terminal
P in : M S , T T 1 , T T 2 , O S C
V
DD
P in : X IN 0 ~ X IN 7 , Z IN 0 ~ Z IN 3 ( w ith p u ll- h ig h r e s is to r )
V
DD
V
DD
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HT6230
* Output terminal
P in : D R S 0 ~ D R S 7
ENB D A T A IN
P in : C O D E , M C O D E
V
DD
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V Input Voltage .................VSS-0.3V to VDD+0.3V Storage Temperature.................-50C to 125C Operating Temperature ..............-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Electrical Characteristics
Symbol VDD VOL1 VOL2 VOH RPH Parameter Supply Voltage DRS0~DRS7 Output Voltage Low CODE, MCODE Output Voltage Low CODE, MCODE Output Voltage High XIN0~XIN7 and ZIN0~ZIN3 Pull-high Oscillator Frequency Operational Free-running Test Conditions VDD 3/4 3V 3V 3V 3V Conditions 3/4 IOL1=0.3mA IOL2=0.6mA IOH=-0.4mA TT1=TT2=MS=Low VI=0V 3/4 3V 3/4 30 50 100 Min. 2.4 3/4 3/4 VDD-0.3 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 27 429
Ta=25C Max. Unit 5.2 0.3 0.3 3/4 3/4 3/4 V V V V kW kHz kHz
fOSC
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Functional Description
Key operation When MS is low, the legal key operation is that only one ZIN or XIN can be connected to one DRS driver and if more than one XIN, ZIN or both are pressed at the same time then the key operation is recognized as illegal; hence, the oscillator will not start. When MS is high, the legal key operation is that exactly one ZIN and one XIN are connected to two DRS drivers and other cases of key operation are all considered as illegal. However, when one XIN or ZIN is connected to more than one DRS, the last key scan driver is to generate output data code. Format of transmission code The output pin CODE transmits the data code as a code format, as shown at the bottom figure. The method of transmitting one code bit is called biphase transmission and is represented by the following fig: cent state both CODE and MCODE are high impedance. Key scan drivers The key scan drivers DRS0 to DRS7 are open drain NMOS and the outputs of these are all low in quiescent state. When a legal key operation is detected, the debounce cycle starts and at the end of the debounce cycle, the DRS outputs are high impedance. Furthermore, the scanning cycle starts and DRS outputs take turns to switch to low state. Programmable output data code The output data code corresponding to each key is programmable by hardware mask option. The PAL circuit is necessary for this purpose. Operation mode
* One-key system mode
lo g ic 0
lo g ic 1
8
Where one code bit time is 32 TOSC. The output signal of the MCODE pin is the signal of the generated output code modulated by 1/12 of the system frequency with 1/4 duty cycle. In quiesone code 1 D e b o u n c e c y c le ( 1 6 b it- tim e ) S can c y c le S ta rt b its 1 MSB
The device enters this mode by switching the MS input pin to low state. The pull-high resistors are connected to all XIN and ZIN inputs so that all sense inputs are at high state, until pulled to low state by key operation. In this mode the legal key operation is that only one ZIN or XIN can be connected to one DRS. When a sense input detects a low level, an enable signal is generated to latch the system or command latches. If the sense input belongs to ZIN, the corresponding system code is generated and the command code is defined as all
LSB 5 s y s te m b its
MSB 6 c o m m a n d b its
LSB
s ta rt
C o n tro l b it
Code 1 s ta rt 1 6 b it- tim e 4 8 b it- tim e R e p e titio n tim e ( 6 4 b it- tim e )
Code 2 1 6 b it- tim e
Transmission code format
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logic 1. If the sense input comes from XIN, the corresponding command code together with the system code stored in the system latches are generated.
* Two-key system mode * During Tsep and debounce time, the device
will reset immediately if a key is released.
* During Scan cycle in Tcode, a reset will occur
The device goes into this mode by switching the MS input pin to high state. The pull-high resistors are only connected to XIN inputs except the first scan cycle. In the first scan cycle, there only exists pull-high resistors in ZIN inputs. In this mode, the legal key operation is that exactly one XIN and one ZIN are connected to two DRS drivers. In the first scan duration, it detects which key in Z-key matrix is pressed and generates an enable signal to latch the system latches. While in the second scan duration, it detects which key in the X-key matrix is pressed and generates an enabled signal to latch the command latches. After being latched, the system and command codes are transmitted. Control bit A control bit is added after two start bits and will be complemented if one key is released. The decoder can decide whether the next code is a new command or not. Oscillator The embedded part of the oscillator is an RC-oscillation circuit. The OSC pin is the input terminal of the RC-oscillation circuit and is connected to an external ceramic resonator (429kHz). A resistor of 6.8kW must be in series with the resonator. The resonator and resistor are grounded at one side. Reset (after key release) In a complete code repetition time, as shown in the figure below, the following situation of key release results in a reset action.
Code 1 Tcode Tsep R e p e titio n tim e D ebounce tim e Code 2 Tcode
if a key is released in three cases described below: When one of the key scan drivers is in the low state Before that key has been detected When MS is high and there is no wired connection in Z-key matrix
Test pins (TT1 and TT2) There are four modes by the combination of TT1 and TT2. TT1 0 1 1 0 TT2 0 1 0 1 Reset Test mode 1 Test mode 2 Mode Normal mode
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Application Circuits
V 1 2 V
DD
DD
X IN 7 3 4 MS Z IN 0 5 6 Z IN 1 Z IN 2 7 8 9 Z IN 3 MCODE CODE DRS7 DRS6 DRS5 DRS4 DRS3 VSS
VDD X IN 6 X IN 5 X IN 4 X IN 3 X IN 2 X IN 1 X IN 0 TT1 TT2 OSC DRS0 DRS1 DRS2
28 27 26 25 24 23 22 21 20 19 18 17 16 15 R e s o n a to r (4 2 9 k H z ) 6 .8 k 9
In fra -R e d 479 1k9
10 11 12 13 14
HT6230 28 SO P
w h e re
p u s h - b u tto n s w itc h
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Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright O 2000 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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